Some conventional timer circuits use a counter circuit to time out specific time intervals. The counter circuit increments a counter value at known, fixed time increments, e.g., according to a clock signal or a divided clock signal. To time out a specified time interval, the counter circuit determines a threshold count equal to the duration of the specified time interval divided by the fixed time increment. The counter circuit compares the threshold count to the counter value while incrementing the counter value, and when the counter value reaches the threshold count, the timer circuit determines that the specified time interval has passed.
A counter circuit can generate a pulse width modulated signal using a waveform generator. The duty cycle and frequency of the pulse width modulated signal specify that the signal should be at a logic high level during a specified time interval and a logic low level until the end of timer period (counter overflow). The waveform generator generates the signal using the counter circuit to time out the first time interval and timer periods (counter overflow).